MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 656

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Debug Support
32-12
12–11
9–8
Bit
15
14
13
10
7
6
5
Name
MAP
EMU
DDC
TRC
UHE
BTB
NPL
IPI
—
Table 32-8. CSR Field Descriptions (Continued)
Force processor references in emulator mode.
0 All emulator-mode references are mapped into supervisor code and data spaces.
1 The processor maps all references while in emulator mode to a special address space,
Force emulation mode on trace exception. If TRC = 1, the processor enters emulator mode
when a trace exception occurs. If TRC=0, the processor enters supervisor mode.
Force emulation mode. If EMU = 1, the processor begins executing in emulator mode. See
Section 32.6.1.1, “Emulator
Debug data control. Controls operand data capture for DDATA, which displays the number
of bytes defined by the operand reference size before the actual data; byte displays 8 bits,
word displays 16 bits, and long displays 32 bits (one nibble at a time across multiple
PSTCLK cycles). See
00 No operand data is displayed.
01 Capture all write data.
10 Capture all read data.
11 Capture all read and write data.
User halt enable. Selects the CPU privilege level required to execute the HALT instruction.
0 HALT is a supervisor-only instruction.
1 HALT is a supervisor/user instruction.
Branch target bytes. Defines the number of bytes of branch target address DDATA
displays.
00 0 bytes
01 Lower 2 bytes of the target address
10 Lower 3 bytes of the target address
11 Entire 4-byte target address
See
Reserved, should be cleared.
Non-pipelined mode. Determines whether the core operates in pipelined mode or not.
0 Pipelined mode
1 Nonpipelined mode. The processor effectively executes one instruction at a time with
Regardless of the NPL state, a triggered PC breakpoint is always reported before the
triggering instruction executes. In normal pipeline operation, the occurrence of an address
and/or data breakpoint trigger is imprecise. In non-pipeline mode, triggers are always
reported before the next instruction begins execution and trigger reporting can be
considered precise.
Ignore pending interrupts.
1 Core ignores any pending interrupt requests signalled while in single-instruction-step
mode.
0 Core services any pending interrupt requests that were signalled while in single-step
mode.
TT = 10, TM = 101 or 110.
no overlap. This adds at least 5 cycles to the execution time of each instruction. Given
an average execution latency of 1.6 cycles/instruction, throughput in non-pipeline mode
would be 6.6 cycles/instruction, approximately 25% or less of pipelined performance.
Section 32.3.1, “Begin Execution of Taken Branch (PST = 0x5).”
MCF5235 Reference Manual, Rev. 2
Table
Mode.”
32-2.
Description
Freescale Semiconductor