MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 470

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

FlexCAN
21.3.2.6 FlexCAN Error and Status Register (ERRSTATn)
ERRSTATn reflects various error conditions, some general status of the device, and is the source
of three interrupts to the CPU. The reported error conditions (bits 15:10) are those occurred since
the last time the CPU read this register. The read action clears bits 15-10. Bits 9–3 are status bits.
Most bits in this register are read only, except for BOFFINT and ERRINT, which are interrupt
flags that can be cleared by writing 1 to them. Writing 0 has no effect. Refer to
“Interrupts.”
21-16
Reg Addr
Reset
Reset
31–16
15–8
Bits
Bits
7–0
15
14
W
W
R
R BIT1
ERR
31
15
0
0
0
RXECTR
BIT1ERR
BIT0ERR
TXECTR
Figure 21-9. FlexCAN Error and Status Register (ERRSTATn)
Name
Name
BIT0
ERR
—
30
14
0
0
0
Table 21-6. ERRCNTn Field Descriptions (Continued)
ACK
ERR
29
13
0
0
0
Receive error counter. Indicates current number of receive errors.
Transmit error counter. Indicates current number of transmit errors.
Reserved, should be cleared.
Bit1 error. Indicates inconsistency between the transmitted and received bit in a message.
0 No transmit bit error
1 At least one bit sent as recessive was received as dominant
Note: The transmit bit error field is not modified during the arbitration field or the ACK slot
bit time of a message, or by a transmitter that detects dominant bits while sending a
passive error frame.
Bit0 error. Indicates inconsistency between the transmitted and received bit in a message.
0 No transmit bit error
1 At least one bit sent as dominant was received as recessive
Table 21-7. ERRSTATn Field Descriptions
CRC
ERR
28
12
0
0
0
IPSBAR + 0x1C_0020 (CAN0); 0x1F_0020 (CAN1)
MCF5235 Reference Manual, Rev. 2
FRM
ERR
27
11
0
0
0
ERR
STF
26
10
0
0
0
WRN
TX
25
0
0
9
0
WRN
RX
24
0
0
0
8
Description
Description
IDLE TXRX
23
0
0
7
0
22
0
0
0
6
21
0
0
5
CONF
0
FLT
20
0
0
0
4
19
0
0
0
0
3
Freescale Semiconductor
BOFF
INT
18
0
0
0
2
Section 21.5.1,
ERR
INT
17
0
0
0
1
16
0
0
0
0
0