MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 581

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

27.6
The following examples show programming for initialization, signaling START, post-transfer
software response, signalling STOP, and generating a repeated START.
27.6.1 Initialization Sequence
Before the interface can transfer serial data, registers must be initialized, as follows:
Freescale Semiconductor
1. Set I2FDR[IC] to obtain I2C_SCL frequency from the system bus clock. See
2. Update the I2ADR to define its slave address.
3. Set I2CR[IEN] to enable the I
4. Modify the I2CR to select or deselect master/slave mode, transmit/receive mode, and
Section 27.5.2, “I2C Frequency Divider Register
interrupt-enable or not.
7–0
Bit
I
2
C Programming Examples
If I2SR[IBB] is set when the I
following pseudocode sequence before proceeding with normal
initialization code. This issues a STOP command to the slave device,
placing it in idle state as if it were just power-cycled on.
Name
DATA
I2CR = 0x0
I2CR = 0xA0
dummy read of I2DR
I2SR = 0x0
I2CR = 0x0
I
initiated. The most significant bit is sent first. In master receive mode, reading this register
initiates the reception of the next byte of data. In slave mode, the same functions are
available after an address match has occurred.
Note: 1. In master transmit mode, the first byte of data written to I2DR following assertion
of I2CR[MSTA] is used for the address transfer and should comprise the calling address
(in position D7–D1) concatenated with the required R/W bit (in position D0). This bit (D0)
is not automatically appended by the hardware, software must provide the appropriate
R/W bit.
Note: 2. I2CR[MSTA] generates a start when a master does not already own the bus.
I2CR[RSTA] generates a start (restart) without the master first issuing a stop (i.e., the
master already owns the bus). In order to start the read of data, a dummy read to this
register starts the read process from the slave. The next read of the I2DR register contains
the actual data.
2
C data. In master transmit mode, when data is written to this register, a data transfer is
Table 27-6. I2DR Field Description
MCF5235 Reference Manual, Rev. 2
2
C bus interface system.
2
NOTE
C bus module is enabled, execute the
Description
(I2FDR).”
I
2
C Programming Examples
27-13