MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 17

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

19.1.5
19.1.5.1
19.1.5.2
19.1.6
19.1.7
19.2
19.2.1
19.2.2
19.2.3
19.2.4
19.2.4.1
19.2.4.2
19.2.4.3
19.2.4.4
19.2.4.5
19.2.4.6
19.2.4.7
19.2.4.8
19.2.4.9
19.2.4.10
19.2.4.11
19.2.4.12
19.2.4.13
19.2.4.14
19.2.4.15
19.2.4.16
19.2.4.17
19.2.4.18
19.2.4.19
19.2.4.20
19.2.4.21
19.2.4.22
19.2.4.23
19.2.5
19.2.5.1
19.2.5.2
19.2.5.3
19.3
19.3.1
19.3.1.1
19.3.2
Freescale Semiconductor
Paragraph
Number
Memory Map/Register Definition ................................................................................ 19-5
Functional Description ................................................................................................ 19-35
Interface Options ....................................................................................................... 19-4
Address Recognition Options ................................................................................... 19-5
Internal Loopback ..................................................................................................... 19-5
High-Level Module Memory Map ........................................................................... 19-5
Register Memory Map .............................................................................................. 19-6
MIB Block Counters Memory Map .......................................................................... 19-6
Register Description ................................................................................................. 19-8
Buffer Descriptors ................................................................................................... 19-29
Initialization Sequence ............................................................................................ 19-35
User Initialization (Prior to Setting ECRn[ETHER_EN]) ...................................... 19-36
10 Mbps and 100 Mbps MII Interface .................................................................. 19-4
10 Mpbs 7-Wire Interface Operation .................................................................... 19-5
Ethernet Interrupt Event Register (EIR) ............................................................... 19-9
Interrupt Mask Registers (EIMR0 & EIMR1) .................................................... 19-10
Receive Descriptor Active Registers (RDAR0 & RDAR1) ............................... 19-11
Transmit Descriptor Active Registers (TDAR0 & TDAR1) .............................. 19-12
Ethernet Control Registers (ECR0 & ECR1) ..................................................... 19-13
MII Management Frame Registers (MMFR0 & MMFR1) ................................ 19-14
MII Speed Control Registers (MSCR0 & MSCR1) ........................................... 19-16
MIB Control Registers (MIBC0 & MIBC1) ...................................................... 19-17
Receive Control Registers (RCR0 & RCR1) ...................................................... 19-18
Driver/DMA Operation with Buffer Descriptors ............................................... 19-29
Ethernet Receive Buffer Descriptors (RxBD0 & RxBD1) ................................. 19-31
Ethernet Transmit Buffer Descriptors (TxBD0 & TxBD1) ................................ 19-33
Hardware Controlled Initialization ..................................................................... 19-35
Physical Address High Registers (PAUR0 & PAUR1) ..................................... 19-21
Descriptor Group Lower Address Registers (GALR0 & GALR1) .................. 19-24
FIFO Transmit FIFO Watermark Registers (TFWR0 & TFWR1) .................... 19-25
FIFO Receive Bound Registers (FRBR0 & FRBR1) ........................................ 19-25
FIFO Receive Start Registers (FRSR0 & FRSR1) ............................................ 19-26
Transmit Control Registers (TCR0 & TCR1) ................................................... 19-19
Physical Address Low Registers (PALR0 & PALR1) ...................................... 19-20
Opcode/Pause Duration Registers (OPD0 & OPD1) ......................................... 19-21
Descriptor Individual Lower Address Registers (IALR0 & IALR1) ................ 19-23
Descriptor Group Upper Address Registers (GAUR0 & GAUR1) ................... 19-23
Receive Descriptor Ring Start Registers (ERDSR0 & ERDSR1) ..................... 19-27
Transmit Buffer Descriptor Ring Start Registers (ETSDR0 & ETSDR1) ....... 19-27
Receive Buffer Size Registers (EMRBR0 & EMRBR1) .................................. 19-28
Descriptor Individual Upper Address Registers (IAUR0 & IAUR1) ............... 19-22
MCF5235 Reference Manual, Rev. 2
Contents
Title
Number
Page
xvii