MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 663

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

32.5
The ColdFire Family implements a low-level system debugger in the microprocessor hardware.
Communication with the development system is handled through a dedicated, high-speed serial
command interface. The ColdFire architecture implements the BDM controller in a dedicated
hardware module. Although some BDM operations, such as CPU register accesses, require the
CPU to be halted, other BDM commands, such as memory accesses, can be executed while the
processor is running.
32.5.1
Although most BDM operations can occur in parallel with CPU operations, unrestricted BDM
operation requires the CPU to be halted. The sources that can cause the CPU to halt are listed
below in order of priority:
The assertion of BKPT should be considered in the following two special cases:
Freescale Semiconductor
1. A catastrophic fault-on-fault condition automatically halts the processor.
2. A hardware breakpoint can be configured to generate a pending halt condition similar to
3. The execution of a HALT instruction immediately suspends execution. Attempting to
4. The assertion of the BKPT input is treated as a pseudo-interrupt; that is, the halt condition
• After the system reset signal is negated, the processor waits for 16 processor clock cycles
the assertion of BKPT. This type of halt is always first made pending in the processor.
Next, the processor samples for pending halt and interrupt conditions once per instruction.
When a pending condition is asserted, the processor halts execution at the next sample
point. See
execute HALT in user mode while CSR[UHE] = 0 generates a privilege violation
exception. If CSR[UHE] = 1, HALT can be executed in user mode. After HALT executes,
the processor can be restarted by serial shifting a
Execution continues at the instruction after HALT.
is postponed until the processor core samples for halts/interrupts. The processor samples
for these conditions once during the execution of each instruction. If there is a pending
halt condition at the sample time, the processor suspends execution and enters the halted
state.
before beginning reset exception processing. If the BKPT input is asserted within eight
cycles after RSTI is negated, the processor enters the halt state, signaling halt status (0xF)
on the PST outputs. While the processor is in this state, all resources accessible through the
debug module can be referenced. This is the only chance to force the processor into
emulation mode through CSR[EMU].
After system initialization, the processor’s response to the
of BDM commands performed while it is halted for a breakpoint. Specifically, if the PC
register was loaded, the
ColdFire Background Debug Mode (BDM)
CPU Halt
Section 32.6.1, “Theory of
GO
MCF5235 Reference Manual, Rev. 2
command causes the processor to exit halted state and pass
Operation.”
GO
command into the debug module.
GO
ColdFire Background Debug Mode (BDM)
command depends on the set
32-19