MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 574

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

I
1
27.4.7 Clock Synchronization and Arbitration
I
more masters devices simultaneously request control of the bus, a clock synchronization
procedure determines the bus clock. Because wire-AND logic is performed on the I2C_SCL line,
a high-to-low transition on the I2C_SCL line affects all the devices connected on the bus. The
devices start counting their low period and once a device’s clock has gone low, it holds the
I2C_SCL line low until the clock high state is reached. However, the change of low to high in this
device clock may not change the state of the I2C_SCL line if another device clock is still within
27-6
2
2
C Interface
C is a true multi-master bus that allows more than one master to be connected to it. If two or
Note: No acknowledge on the last byte
• The first example in
• The second example in
• In the third example in
Example 1:
Example 2:
Example 3:
ST
slave-receiver. The transfer direction is not changed.
first byte. At the moment of the first acknowledge, the master-transmitter becomes a
master-receiver and the slave-receiver becomes slave-transmitter.
repeated using the repeated START signal. This is to communicate with same slave in a
different mode without releasing the bus. The master transmits data to the slave first, and
then the master reads data from slave by reversing the R/W bit.
7-bit Slave
Address
ST
ST
ST = Start
SP = Stop
A = Acknowledge (I2C_SDA low)
A = Not Acknowledge (I2C_SDA high)
Rept ST = Repeated Start
7bit Slave Address
7bit Slave Address
R/W
1
Figure 27-6. Data Transfer, Combined Format
Master Transmits to Slave
A
Figure 27-6
DATA
Figure 27-6
Figure 27-6
MCF5235 Reference Manual, Rev. 2
R/W
R/W
0
1
A/A
A
A
is the case of master-transmitter transmitting to
Rept
ST
the START condition and slave address are both
Register Address
is the master reading the slave immediately after the
DATA
7-bit Slave 0
Address
From Master to Slave
From Slave to Master
R/W
A
A
A
DATA
DATA
Master Reads from Slave
DATA
A/A
A
SP
SP
A
Freescale Semiconductor
DATA A/A
SP