MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 521

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

25.2.3 Transfer Delays
The QSPI supports programmable delays for the QSPI_CS signals before and after a transfer. The
time between QSPI_CS assertion and the leading QSPI_CLK edge, and the time between the end
of one transfer and the beginning of the next, are both independently programmable.
The chip select to clock delay enable bit in command RAM, QCR[DSCK], enables the
programmable delay period from QSPI_CS assertion until the leading edge of QSPI_CLK.
QDLYR[QCD] determines the period of delay before the leading edge of QSPI_CLK. The
following expression determines the actual delay before the QSPI_CLK leading edge:
QDLYR[QCD] has a range of 1–127.
When QDLYR[QCD] or QCR[DSCK] equals zero, the standard delay of one-half the QSPI_CLK
period is used.
The command RAM delay after transmit enable bit, QCR[DT], enables the programmable delay
period from the negation of the QSPI_CS signals until the start of the next transfer. The delay after
transfer can be used to provide a peripheral deselect interval. A delay can also be inserted between
consecutive transfers to allow serial A/D converters to complete conversion. There are two
transfer delay options: the user can choose to delay a standard period after serial transfer is
complete or can specify a delay period. Writing a value to QDLYR[DTL] specifies a delay period.
QCR[DT] determines whether the standard delay period (DT = 0) or the specified delay period
(DT = 1) is used. The following expression is used to calculate the delay:
where QDLYR[DTL] has a range of 1–255.
A zero value for DTL causes a delay-after-transfer value of 8192/f
Freescale Semiconductor
Table 25-2. QSPI_CLK Frequency as Function of Internal Bus Clock and Baud Rate
QSPI_CS-to-QSPI_CLK delay = QDLYR[QCD]/f
Delay after transfer = 32 × QDLYR[DTL] /f
Standard delay after transfer = 17/f
QMR [BAUD]
MCF5235 Reference Manual, Rev. 2
255
16
32
2
4
8
sys/2
Internal Bus Clock
(DT = 0)
18.75 MHz
9.375 MHz
4.688 MHz
2.344 MHz
1.172 MHz
147.1 kHz
75 MHz
sys/2
sys/2
(DT = 1)
sys/2
.
Operation
25-7