MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 507

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

24.2.7 DMA Timer Extended Mode Registers (DTXMRn)
DTXMRn, shown in
Freescale Semiconductor
Bits
Bits
2–1
5
4
3
0
7
Figure 24-3. DMA Timer Extended Mode Registers (DTXMRn)
DMAEN
Name
Name
ORRI
Address
FRR
RST
CLK
OM
Reset
Table 24-2. DTMRn Field Descriptions (Continued)
Figure
W
R DMAEN
Output mode.
0 Active-low pulse for one system clock cycle (13-ns resolution at 75 MHz).
1 Toggle output.
Output reference request, interrupt enable. If ORRI is set when DTERn[REF] = 1, a DMA
request or an interrupt occurs, depending on the value of DTXMRn[DMAEN] (DMA request
if =1, interrupt if =0).
0 Disable DMA request or interrupt for reference reached (does not affect DMA request
1 Enable DMA request or interrupt upon reaching the reference value.
Free run/restart
0 Free run. Timer count continues to increment after reaching the reference value.
1 Restart. Timer count is reset immediately after reaching the reference value.
Input clock source for the timer
00 Stop count
01 System clock divided by 1
10 System clock divided by 16. Note that this clock source is not synchronized with the
11 DTINn pin (falling edge)
Reset timer. Performs a software timer reset similar to an external reset, although other
register values can still be written while RST = 0. A transition of RST from 1 to 0 resets
register values. The timer counter is not clocked unless the timer is enabled.
0 Reset timer (software reset)
1 Enable timer
DMA request. Enables DMA request output on counter reference match or capture edge
0 DMA request disabled
1 DMA request enabled
IPSBAR + 0x00_0402 (DTXMR0); IPSBAR + 0x00_0442 (DTXMR1);
IPSBAR + 0x00_0482 (DTXMR2); IPSBAR + 0x00_04C2 (DTXMR3)
or interrupt on capture function).
0
Table 24-3.
event.
7
timer; thus successive time-outs may vary slightly.
24-3, program DMA request and increment modes for the timers.
6
0
0
MCF5235 Reference Manual, Rev. 2
DTXMR
0
0
5
0
0
4
n Field Descriptions
Description
Description
0
0
3
0
0
2
0
0
1
MODE16
Memory Map/Register Definition
0
0
24-5