MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 451

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Freescale Semiconductor
29–24
Bits
31
30
23
Name
Read:
Read:
Read:
DTRS
DTRC
Write:
Write:
Write:
CIOS
CIOC
CIS
CIC
—
Table 20-21. ETPU_CnSCR Field Descriptions
Channel interrupt status.
0 Channel has no pending interrupt to the MCF5235 ColdFire core.
1 Channel has a pending interrupt to the MCF5235 ColdFire core.
CIS and CIC are mirrored in the ETPU_CISR. For more information on ETPU_CISR and
interrupts, see
(ETPU_CISR),” and the eTPU User’s Manual.
Channel interrupt clear.
0 Keep interrupt status bit unaltered.
1 Clear interrupt status bit.
CIS and CIC are mirrored in the ETPU_CISR. For more information on ETPU_CISR and
interrupts, see
(ETPU_CISR),” and eTPU User’s Manual.
Channel interrupt overflow status.
0 Interrupt overflow negated for this channel
1 Interrupt overflow asserted for this channel
CIOS and CIOC are mirrored in the ETPU_CIOSR. For more information on the
ETPU_CIOSR and interrupt overflow, see
Overflow Status Register
Channel interrupt overflow clear.
0 Keep status bit unaltered.
1 Clear status bit.
CIOS and CIOC are mirrored in the ETPU_CIOSR. For more information on the
ETPU_CIOSR and interrupt overflow, see
Overflow Status Register
Reserved.
Data transfer request status.
0 Channel has no pending data transfer request.
1 Channel has a pending data transfer request.
DTRS and DTRC are mirrored in the ETPU_CISR. For more information on the
ETPU_CISR and data transfer, see
Request Status Register
Data transfer request clear.
0 Keep status bit unaltered
1 Clear status bit.
DTRS and DTRC are mirrored in the ETPU_CISR. For more information on the
ETPU_CISR and data transfer, see
Request Status Register
MCF5235 Reference Manual, Rev. 2
Section 20.6.2.3.1, “eTPU Channel Interrupt Status Register
Section 20.6.2.3.1, “eTPU Channel Interrupt Status Register
(ETPU_CDTRSR).” and the eTPU User’s Manual.
(ETPU_CDTRSR).” and the eTPU User’s Manual.
(ETPU_CIOSR).” and the eTPU User’s Manual
(ETPU_CIOSR).” and the eTPU User’s Manual
Section 20.6.2.3.2, “eTPU Channel Data Transfer
Section 20.6.2.3.2, “eTPU Channel Data Transfer
Description
Section 20.6.2.3.3, “eTPU Channel Interrupt
Section 20.6.2.3.3, “eTPU Channel Interrupt
Memory Map/Register Definition
20-37