MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 292

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

DMA Controller Module
DSRn[DONE], shown in
When a transfer sequence is initiated and BCRn[BCR] is not a multiple of 16, 4, or 2 when the
DMA is configured for line, longword, or word transfers, respectively, DSRn[CE] is set and no
transfer occurs. See
14.3.4.1 DMA Status Registers (DSR0–DSR3)
In response to an event, the DMA controller writes to the appropriate DSRn bit,
a write to DSRn[DONE] results in action.
14-8
Bits
7
6
5
4
3
2
Name
REQ
BES
BED
Address
CE
—
—
Reset
Section 14.3.4.1, “DMA Status Registers
W
R
Reserved, should be cleared.
Configuration error. Occurs when BCR, SAR, or DAR does not match the requested
transfer size, or if BCR = 0 when the DMA receives a start condition. CE is cleared at
hardware reset or by writing a 1 to DSR[DONE].
0 No configuration error exists.
1 A configuration error has occurred.
Bus error on source
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the read portion of a transfer.
Bus error on destination
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the write portion of a transfer.
Reserved, should be cleared.
Request
0 No request is pending or the channel is currently active. Cleared when the channel is
1 The DMA channel has a transfer remaining and the channel is not selected.
Figure 14-7. DMA Status Registers (DSRn)
Figure
selected.
0
0
7
Table 14-3. DSRn Field Descriptions
14-7, is set when the block transfer is complete.
CE
MCF5235 Reference Manual, Rev. 2
0
6
BES
0
5
See
BED
0
4
Figure 14-6
Description
0
0
3
REQ
(DSR0–DSR3).”
2
0
BSY
0
1
DONE
0
0
Freescale Semiconductor
Figure
14-7. Only