MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 486

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

FlexCAN
21.5 FlexCAN Initialization Sequence
Initialization of the FlexCAN includes the initial configuration of the message buffers and
configuration of the CAN communication parameters following a reset, as well as any
reconfiguration which may be required during operation. The FlexCAN module may be reset in
three ways:
Soft reset is synchronous and has to follow an internal request/acknowledge procedure across
clock domains. Therefore, it may take some time to fully propagate its effects. The
CANMCRn[SOFT_RST] bit remains asserted while soft reset is pending, so software can poll this
bit to know when the reset has completed. Also, soft reset can not be applied while clocks are shut
down in any of the low power modes. The low power mode should be exited and the clocks
resumed before applying soft reset.
The clock source, CANCTRLn[CLK_SRC], should be selected while the module is in disable
mode. After the clock source is selected and the module is enabled (CANMCRn[MDIS] bit
cleared), the FlexCAN automatically enters freeze mode. In freeze mode, the FlexCAN is
un-synchronized to the CAN bus, the CANMCRn register’s HALT and FRZ bits are set, the
internal state machines are disabled, and the CANMCRn register’s FRZ_ACK and NOT_RDY
bits are set. The CANnTX pin is in recessive state and the FlexCAN does not initiate any
transmission or reception of CAN frames. Note that the message buffers are not affected by reset,
so they are not automatically initialized.
21-32
• Device level hard resetwhich resets all memory mapped registers asynchronously
• Device level soft reset, which resets some of the memory mapped registers synchronously
• CANMCRn[SOFT_RST] bit, which has the same effect as the device level soft reset
(refer to
Table 21-16. CAN Standard Compliant Bit Time Segment Settings
Table 21-1
Time Segment 1
5 .. 10
4 .. 11
5 .. 12
6 .. 13
7 .. 14
8 .. 15
9 .. 16
to see which registers are affected by soft reset)
MCF5235 Reference Manual, Rev. 2
Time Segment 2
2
3
4
5
6
7
8
Re-synchronization
Jump Width
1 .. 3
1 .. 2
1 .. 4
1 .. 4
1 .. 4
1 .. 4
1 .. 4
Freescale Semiconductor