MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 90

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

ColdFire Core
10 and 11, respectively. The V2 core does not provide illegal instruction detection on the extension
words on any instruction, including MOVEC.
3.7.4
Attempting to divide by zero causes an exception (vector 5, offset = 0x014).
3.7.5
The attempted execution of a supervisor mode instruction while in user mode generates a privilege
violation exception. See the ColdFire Programmer’s Reference Manual for lists of supervisor- and
user-mode instructions.
3.7.6
To aid in program development, all ColdFire processors provide an instruction-by-instruction
tracing capability. While in trace mode, indicated by the assertion of the T-bit in the status register
(SR[15] = 1), the completion of an instruction execution (for all but the STOP instruction) signals
a trace exception. This functionality allows a debugger to monitor program execution.
The STOP instruction has the following effects:
If the processor is not in trace mode and executes a STOP instruction where the immediate operand
sets SR[T], hardware loads the SR and generates a trace exception. The PC in the exception stack
frame points to the instruction after the STOP, and the SR reflects the value loaded in step 2.
Because ColdFire processors do not support any hardware stacking of multiple exceptions, it is the
responsibility of the operating system to check for trace mode after processing other exception
types. As an example, consider the execution of a TRAP instruction while in trace mode. The
processor will initiate the TRAP exception and then pass control to the corresponding handler. If
the system requires that a trace exception be processed, it is the responsibility of the TRAP
exception handler to check for this condition (SR[15] in the exception stack frame asserted) and
pass control to the trace handler before returning from the original exception.
3-14
1. The instruction before the STOP executes and then generates a trace exception. In the
2. When the trace handler is exited, the STOP instruction is executed, loading the SR with
3. The processor then generates a trace exception. The PC in the exception stack frame
exception stack frame, the PC points to the STOP opcode.
the immediate operand from the instruction.
points to the instruction after the STOP, and the SR reflects the value loaded in the
previous step.
Divide-By-Zero
Privilege Violation
Trace Exception
MCF5235 Reference Manual, Rev. 2
Freescale Semiconductor