MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 649

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

32.3.1
PST is 0x5 when a taken branch is executed. For some opcodes, a branch target address may be
displayed on DDATA depending on the CSR settings. CSR also controls the number of address
bytes displayed, which is indicated by the PST marker value immediately preceding the DDATA
nibble that begins the data output.
Bytes are displayed in least-to-most-significant order. The processor captures only those target
addresses associated with taken branches which use a variant addressing mode, that is, RTE and
RTS instructions, JMP and JSR instructions using address register indirect or indexed addressing
modes, and all exception vectors.
The simplest example of a branch instruction using a variant address is the compiled code for a C
language case statement. Typically, the evaluation of this statement uses the variable of an
expression as an index into a table of offsets, where each offset points to a unique case within the
structure. For such change-of-flow operations, the MCF5235 uses the debug pins to output the
following sequence of information on successive processor clock cycles:
Freescale Semiconductor
1. Use PST (0x5) to identify that a taken branch was executed.
2. Using the PST pins, optionally signal the target address to be displayed sequentially on the
3. The new target address is optionally available on subsequent cycles using the DDATA
1000–1011 Indicates the number of bytes to be displayed on the DDATA port on subsequent processor clock cycles.
PST[3:0]
1100
1101
DDATA pins. Encodings 0x9–0xB identify the number of bytes displayed.
port. The number of bytes of the target address displayed on this port is configurable (2, 3,
or 4 bytes).
1110
1111
Begin Execution of Taken Branch (PST = 0x5)
The value is driven onto the PST port one PSTCLK cycle before the data is displayed on DDATA.
1000 Begin 1-byte transfer on DDATA.
1001 Begin 2-byte transfer on DDATA.
1010 Begin 3-byte transfer on DDATA.
1011 Begin 4-byte transfer on DDATA.
Exception processing. Exceptions that enter emulation mode (debug interrupt or optionally trace)
generate a different encoding, as described below. Because the 0xC encoding defines a multiple-cycle
mode, PST outputs are driven with 0xC until exception processing completes.
Entry into emulator mode. Displayed during emulation mode (debug interrupt or optionally trace).
Because this encoding defines a multiple-cycle mode, PST outputs are driven with 0xD until exception
processing completes.
Processor is stopped. Appears in multiple-cycle format when the MCF5235 executes a STOP
instruction. The ColdFire processor remains stopped until an interrupt occurs, thus PST outputs display
0xE until the stopped mode is exited
Processor is halted. Because this encoding defines a multiple-cycle mode, the PST outputs display 0xF
until the processor is restarted or reset. (See
Table 32-2. Processor Status Encoding (Continued)
MCF5235 Reference Manual, Rev. 2
.
Section 32.5.1, “CPU
Definition
Halt.”)
Real-Time Trace Support
32-5