MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 214

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

System Control Module (SCM)
11.2.1.2 Memory Base Address Register (RAMBAR)
The MCF5235 supports dual-ported local SRAM memory. This processor-local memory can be
accessed directly by the core and/or other system bus masters. Since this memory provides
single-cycle accesses at processor speed, it is ideal for applications where double-buffer schemes
can be used to maximize system-level performance. For example, a DMA channel in a typical
double-buffer (also known as a ping-pong scheme) application may load data into one portion of
the dual-ported SRAM while the processor is manipulating data in another portion of the SRAM.
Once the processor completes the data calculations, it begins processing the just-loaded buffer
while the DMA moves out the just-calculated data from the other buffer, and reloads the next data
block into the just-freed memory region. The process repeats with the processor and the DMA
“ping-ponging” between alternate regions of the dual-ported SRAM.
The MCF5235 design implements the dual-ported SRAM in the memory space defined by the
RAMBAR register. There are two physical copies of the RAMBAR register: one located in the
processor core and accessible only via the privileged MOVEC instruction at CPU space address
0xC05, and another located in the SCM at IPSBAR + 0x008. ColdFire core accesses to this
memory are controlled by the processor-local copy of the RAMBAR, while (e.g., DMA, FEC, etc.)
module accesses are enabled by the SCM's RAMBAR.
11-4
Address
Reset
Reset
31–30
29–1
Bits
0
W
W
R
R
—
31
15
0
0
BA
Name
—
30
14
1
0
BA
—
V
Figure 11-1. IPS Base Address Register (IPSBAR)
—
—
29
13
0
0
Base address. Defines the base address of the 1-Gbyte internal peripheral space. This is
the starting address for the IPS registers when the valid bit is set.
Reserved, should be cleared.
Valid. Enables/disables the IPS Base address region. V is set at reset.
0 IPS Base address is not valid.
1 IPS Base address is valid.
—
—
28
12
0
0
Table 11-2. IPSBAR Field Description
—
—
27
11
0
0
MCF5235 Reference Manual, Rev. 2
—
—
26
10
0
0
25
—
—
0
0
9
IPSBAR + 0x000
—
—
24
0
0
8
23
—
—
Description
0
0
7
—
—
22
0
6
0
—
—
21
0
0
5
—
—
20
0
0
4
—
—
19
0
0
3
Freescale Semiconductor
—
—
18
0
0
2
—
—
17
0
0
1
16
—
V
0
1
0