MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 367

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

The RAM is the focal point of all data flow in the Fast Ethernet Controller and is divided into
transmit and receive FIFOs. The FIFO boundaries are programmable using the FRSR register.
User data flows to/from the DMA block from/to the receive/transmit FIFOs. Transmit data flows
from the transmit FIFO into the transmit block and receive data flows from the receive block into
the receive FIFO.
The user controls the FEC by writing, through the SIF (Slave Interface) module, into control
registers located in each block. The CSR (control and status register) block provides global control
(e.g. Ethernet reset and enable) and interrupt handling registers.
The MII block provides a serial channel for control/status communication with the external
physical layer device (transceiver). This serial channel consists of the EMDC (Management Data
Clock) and EMDIO (Management Data Input/Output) lines of the MII interface.
The DMA block provides multiple channels allowing transmit data, transmit descriptor, receive
data and receive descriptor accesses to run independently.
The Transmit and Receive blocks provide the Ethernet MAC functionality (with some assist from
microcode).
The Message Information Block (MIB) maintains counters for a variety of network events and
statistics. It is not necessary for operation of the FEC but provides valuable counters for network
management. The counters supported are the RMON (RFC 1757) Ethernet Statistics group and
some of the IEEE 802.3 counters. See
more information.
19.1.3 Features
The FEC incorporates the following features:
Freescale Semiconductor
• Support for three different Ethernet physical interfaces:
• IEEE 802.3 full duplex flow control
• Programmable max frame length supports IEEE 802.1 VLAN tags and priority
— 100-Mbps IEEE 802.3 MII
— 10-Mbps IEEE 802.3 MII
— 10-Mbps 7-wire interface (industry standard)
DMA references in this section refer to the FEC’s DMA engine. This
DMA engine is for the transfer of FEC data only, and is not related to
the DMA controller described in
Module,” nor to the DMA timers described in
Timers
(DTIM0–DTIM3).”
MCF5235 Reference Manual, Rev. 2
Section 19.2.3, “MIB Block Counters Memory
NOTE
Chapter 14, “DMA Controller
Chapter 24, “DMA
Map” for
Introduction
19-3