HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 100

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Note:
Bits 7 and 6 are cleared to 0 by a reset. Bits 5 to 0 always read 0. When writing to IMVR, write 0
in bits 5 to 0.
4.2.3
The interrupt control register controls the priority order of interrupt sources, and selects the type of
acknowledge cycle and vector output.
Rev. 0, 07/98, page 84 of 453
The codes generated for each interrupt source are listed in table 4.2.
Interrupt Control Register (ITCR)
Interrupt priority
0:
1:
Read/Write
Initial value
Note: Bit 3–bit 0 are reserved. These bits always read 0 and must be set to 0.
Read/Write
Initial value
Bit name
MSCI > DMAC
DMAC > MSCI
Bit name
IMVR7 IMVR6
R/W
IPC
R/W
7
0
7
Acknowledge cycle
00:
01:
10:
11:
0
Non-acknowledge cycle
Single acknowledge cycle
Double acknowledge cycle
Reserved
IAK1
R/W
R/W
6
0
6
0
IAK0
R/W
5
0
5
—
—
0
Modified vector address
R/W
VOS
Hardware-generated code
4
0
4
—
—
0
3
—
—
—
0
3
—
0
Vector output
0:
1:
Interrupt vector register
Interrupt modified vector
—
—
2
—
0
2
—
0
—
—
1
—
0
1
—
0
—
—
—
0
0
—
0
0