HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 227

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

5.5
5.5.1
The advanced digital PLL (ADPLL) extracts clock signals from the receive data and generates a
decoding clock for the receive data.
The ADPLL features:
Figure 5.32 is the block diagram of the ADPLL.
The ADPLL can perform either clock extraction from the receive data or noise suppression for the
receive clock input from the RXC line. In both cases it suppresses the receive data noise.
ADPLL
operating
clock
Clock extraction from five transmission code types (figure 1.8)
Selectable ratio of the ADPLL clock rate to the bit rate
Receive data noise suppression (see section 5.5.2, Operation)
Receive clock noise suppression (see section 5.5.2, Operation)
NRZ
NRZI
Manchester
FM0
FM1
8
16
32
ADPLL
Overview
Receive BRG
output
External clock
(RXC line input)
Receive
data
Figure 5.32 ADPLL Block Diagram
Clock
line 1
Clock
line 2
Multiplexor
Receive clock
Receive data
suppressor
suppressor
noise
noise
Clock extractor
Rev. 0, 07/98, page 211 of 453
delay unit
Data
Noise-suppressed
receive data
Receive data in
phase with the
extracted clock
Extracted clock
Noise-suppressed
receive clock