HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 27

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

1.6.3
Register Name
Mode register 0
Mode register 1
Mode register 2
Control register
RX clock source register
TX clock source register
Time constant register
Command register
Status register 0
Status register 1
Status register 2
Status register 3
Frame status register
Interrupt enable register 0 IE0
Interrupt enable register 1 IE1
Interrupt enable register 2 IE2
Frame interrupt enable
register
Sync/address register 0
Sync/address register 1
Idle pattern register
Notes: 1. These initial values apply after a hardware reset or execution of a channel reset
2. The functions of some bits vary depending on the operating mode (asynchronous, byte
3. When bits 3 and 2 of status register 3 (ST3) are read, the logic level of the CTS and
MSCI Registers (1)
command. Some registers are also initialized to these values by the RX reset command
or TX reset command. See section 5.2, Registers, for details.
synchronous, or bit synchronous). See the register descriptions starting in section 5.2.1.
DCD lines are read.
Symbol Channel 0 Channel 1 Channel 0 Channel 1 MSB
MD0
MD1
MD2
CTL
RXS
TXS
TMC
CMD
ST0
ST1
ST2
ST3
FST
FIE
SA0
SA1
IDL
CPU Modes 0 & 1
2EH
2FH
30H
31H
36H
37H
35H
2CH
22H
23H
24H
25H
26H
28H
29H
2AH
2BH
32H
33H
34H
4EH
4FH
50H
51H
56H
57H
55H
4CH
42H
43H
44H
45H
46H
48H
49H
4AH
4BH
52H
53H
54H
Address
CPU Modes 2 & 3
2FH
2EM
31H
30H
37H
36H
34H
2DH
23H
22H
25H
24H
27H
29H
28H
2BH
2AH
33H
32H
35H
4FH
4EH
51H
50H
57H
56H
54H
4DH
43H
42H
45H
44H
47H
49H
48H
4BH
4AH
53H
52H
55H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
Initial Value at Reset*
Rev. 0, 07/98, page 11 of 453
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
*
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
LSB
1
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
Read/
Write*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2