HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 255

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

6.1
The HD64570 has a four on-chip direct memory access controller channels (DMAC channels
0–3), which support chained-block transfer. Channel 0 is connected to the MSCI channel 0
receiver, channel 1 to the MSCI channel 0 transmitter, channel 2 to the MSCI channel 1 receiver,
and channel 3 to the MSCI channel 1 transmitter (figure 1.14). Other than the connection
destination, the specifications for the four channels are identical.
6.1.1
The on-chip DMAC supports the following DMA transfer modes: single-block transfer (single
address) and chained-block transfer (single address). The features and functions of each mode are
summarized as follows:
Single-Block Transfer Mode (Single Address): Data is transferred in byte units from the MSCI
to memory via DMAC channels 0 and 2, or from memory to the MSCI via DMAC channels 1 and
3.
Chained-Block Transfer Mode (Single Address): When the MSCI is in bit synchronous mode,
data is transferred from the MSCI to memory via DMAC channels 0 and 2, or from the MSCI to
memory via DMAC channels 1 and 3. Successive single or multi-frame transfers can be made by
writing and reading data to/from buffers in memory.
The priority of channels 0–3 is program-selectable in either transfer mode above.
6.1.2
The configuration of each DMAC channel is shown in figure 1.3.
Up to 64 Kbytes of data transferred
Up to 16 Mbytes of memory addresses directly accessed
Interrupt generation at DMA transfer completion
Maximum data transfer rate of 11.1 Mbytes/s (at 16.7-MHz operation without wait states
inserted)
Interrupt generation at DMA transfer completion or frame transfer completion
Maximum data transfer rate of 11.1 Mbytes/s (at 16.7-MHz operation without wait states
inserted)
Section 6 Direct Memory Access Controller (DMAC)
Overview
Functions
Configuration and Operation
Rev. 0, 07/98, page 239 of 453