HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 149

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

In other words, RXINT is set to 1 under one of the following conditions:
Bits 5 2: Reserved. These bits always read 0.
Bit 1 (TXRDY: TX Ready): Indicates the transmit buffer status. When the transmitter is enabled
and the data byte count in the transmit buffer is equal to or less than the value set by TX ready
control register 0 (TRC0), this bit is set to 1. When the transmitter is enabled and the data byte
count in the transmit buffer is equal to or greater than the value set by TX ready control register 1
(TRC1) + 1, this bit is cleared. When the transmitter is disabled, this bit is cleared, regardless of
the data byte count in the transmit buffer. This means that the transmit buffer can be written only
while this bit is 1.
A TXRDY interrupt request is issued to the MPU when this bit and the TXRDYE bit of IE0 are
both set to 1. A DMA request is issued to the on-chip DMAC when this bit is set to 1. For details,
see section 5.8.1, Serial Data Transfer by the MPU and DMAC.
The CLMDE bit is set to 1 and no RXD transition has been detected in the ADPLL window
twice successively in FM mode.
The SYNCDE/FLGDE bit is set to 1 and a SYN character or a flag has been detected.
The CDCDE bit is set to 1 and the DCD line level has changed.
The BRKDE/ABTDE/GAPDE bit is set to 1 and a break start, abort, or a GA pattern has been
detected.
The BRKEE/IDLDE bit is set to 1 and a break end or an idle start has been detected.
The EOME bit is set to 1 and the receive frame has ended.
The PMPE/SHRTE bit is set to 1, and the parity/MP bit is set to 1 or a short frame has been
detected.
The PEE/ABTE bit is set to 1 and a parity error or an abort frame has been detected.
The FRMEE/RBITE bit is set to 1 and a framing error or a residual bit frame has been
detected.
The OVRNE bit is set to 1 and an overrun error has been detected.
The CRCEE bit is set to 1 and a CRC error has been detected.
The EOMFE bit is set to 1, the receive frame has ended, and the last character has been read
from the receive buffer (TRB).
Asynchronous/Byte synchronous/Bit synchronous mode
TXRDY = 0: In TX enable state, indicates that the data byte count in the transmit buffer is
equal to or greater than TXF1 + 1 (the value set by the TRC14 TRC10 bits of TRC1 + 1) or
indicates that the data byte count in the transmit buffer is NOT equal to or less than TXF0 (the
value set by the TRC04 TRC00 bits of TRC0) after the data byte count has temporarily been
equal to or greater than TXF1 + 1. This bit is cleared in TX disable state or when an underrun
error has occurred.
Rev. 0, 07/98, page 133 of 453