HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 130

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Bits 1 0 (PMPM1 PMPM0: Parity/Multiprocessor Mode): Specify the multiprocessor (MP)
mode, and whether or not to use the parity check in asynchronous mode. Rewriting these bits
during operation activates the contents of the new setting for subsequent transmit/receive
characters.
5.2.3
Mode register 2 (MD2) specifies the transmission/reception data code type, the ratio of the
advanced digital phase locked loop (ADPLL) operating clock to the bit rate, and the connection
between the transmit/receive data and the TXD/RXD lines. For the ADPLL, see section 5.5,
ADPLL.
This register is reset under either of the following conditions:
Rev. 0, 07/98, page 114 of 453
RXCHR1, RXCHR0 = 1, 1: 5 bits/character
Byte synchronous/Bit synchronous mode
Reserved. These bits always read 0 and must be set to 0.
Asynchronous mode
PMPM1, PMPM0 = 0, 0:
PMPM1, PMPM0 = 0, 1:
PMPM1, PMPM0 = 1, 0:
PMPM1, PMPM0 = 1, 1:
For the parity check and multiprocessor mode (MP) in asynchronous mode, see Parity /MP Bit,
in section 5.3.1, Asynchronous Mode. For commands, see section 5.2.8, MSCI Command
Register.
Byte synchronous/Bit synchronous mode
Reserved. These bits always read 0 and must be set to 0.
Hardware reset
Channel reset command
MSCI Mode Register 2 (MD2)
Appends no parity/MP bit; performs no parity check
Appends an MP bit according to the commands
Appends even parity for parity check
Appends odd parity for parity check