HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 148

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Bit 7 (TXINT: TXINT Interrupt): Indicates whether or not the TXINT interrupt has occurred.
A TXINT interrupt request is issued to the MPU when this bit and the TXINTE bit of interrupt
enable register 0 (IE0) are both 1.
Bit 6 (RXINT: RXINT Interrupt): Indicates whether or not the RXINT interrupt has occurred.
An RXINT interrupt request is issued to the MPU when this bit and the RXINTE bit of IE0 are
both 1.
Rev. 0, 07/98, page 132 of 453
Asynchronous/Byte synchronous/Bit synchronous mode.
TXINT = 0: Indicates that no TXINT interrupt has occurred.
TXINT = 1: Indicates that a TXINT interrupt has occurred.
This bit is set to 1 under the following conditions:
TXINT = UDRN UDRNE + IDL IDLE + CCTS CCTSE
UDRN, IDL, CCTS: Bits 7, 6, and 3 of status register 1 (ST1)
UDRNE, IDLE, CCTSE: Bits 7, 6, and 3 of interrupt enable register 1 (IE1)
In other words, this bit is set to 1 under either of the following conditions:
Asynchronous/Byte synchronous/Bit synchronous mode
RXINT = 0: Indicates that no RXINT interrupt has occurred.
RXINT = 1: Indicates that an RXINT interrupt has occurred.
This bit is set to 1 under the following conditions:
RXINT =
CDCD CDCDE + (BRKD/ABTD/GAPD)
(BRKDE/ABTDE/GAPDE) + (BRKE/IDLD) (BRKEE/IDLDE) +
EOM EOME + (PMP/SHRT) (PMPE/SHRTE) + (PE/ABT)
(PEE/ABTE) + (FRME/RBIT) (FRMEE/RBITE) + OVRN
OVRNE + CRCE CRCEE + EOMF EOMFE
CLMD, SYNCD/FLGD, CDCD, BRKD/ABTD/GAPD, BRKE/IDLD:
Bits 5, 4, 2, 1, and 0 of status register 1 (ST1)
EOM, PMP/SHRT, PE/ABT, FRME/RBIT, OVRN, CRCE:
Bit 7 bit 2 of status register 2 (ST2)
EOMF:
CLMDE, SYNCDE/FLGDE, CDCDE, BRKDE/ABTDE/GAPDE, BRKEE/IDLDE:
Bits 5, 4, 2, 1, and 0 of interrupt enable register (IE1)
EOME, PMPE/SHRTE, PEE/ABTE, FRMEE/RBITE, OVRNE, CRCEE:
Bit 7 bit 2 of interrupt enable register 2 (IE2)
EOMFE:
The UDRNE bit is set to 1 and an underrun error has occurred.
The IDLE bit is set to 1 in idle state.
The CCTSE bit is set to 1 and the CTS line level has changed.
CLMD CLMDE + (SYNCD/FLGD) (SYNCDE/FLGDE) +
Bit 7 of the frame status register (FST)
Bit 7 of the frame interrupt enable register (FIE)