HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 170

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

5.2.16
Interrupt enable register 2 (IE2) enables or disables interrupt requests when the status bits of status
register 2 (ST2) are set to 1. For details on interrupts, see section 5.7, Interrupts.
Rev. 0, 07/98, page 154 of 453
Async
Byte sync
Bit sync HDLC
Read/Write
Initial value
EOM interrupt enable
• Bit synchronous mode
0: Disable
1: Enable
Note: The bits marked with * are reserved. These bits always read 0 and must be set to 0.
MSCI Interrupt Enable Register 2 (IE2)
PMP interrupt enable
• Asynchronous mode
0: Disable
1: Enable
SHRT interrupt enable
• Bit synchronous mode
0: Disable
1: Enable
EOME
R/W
—
7
0
*
SHRTE
PMPE
R/W
—
6
0
*
ABTE
R/W
PEE
—
5
0
PE interrupt enable
• Asynchronous mode
0: Disable
1: Enable
ABT interrupt enable
• Bit synchronous mode
0: Disable
1: Enable
*
FRME interrupt enable
• Asynchronous mode
0: Disable
1: Enable
RBIT interrupt enable
• Bit synchronous mode
0: Disable
1: Enable
FRMEE
RBITE
R/W
—
4
0
*
OVRNE
R/W
3
0
CRCEE
R/W
—
2
0
OVRN interrupt enable
0: Disable
1: Enable
*
—
—
CRCE interrupt enable
• Byte/Bit synchronous mode
0: Disable
1: Enable
1
0
*
—
—
0
0
*