HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 317

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Table 6.12 Interrupt Types, Interrupt Sources, and Clearing Procedures
Type
Error
interrupt
(DMIA)*
Normal
end
interrupt
(DMIB)*
FCT:
CDA: Current descriptor address register
EDA: Error descriptor address register
Notes: 1. Interrupts, once issued, continue to be requested also in DMA initial state or halt state.
6.6
When the DMAC is reset, the following steps occur.
The DMAC enters DMA initial state
Channel priority becomes 0 > 1 > 2 > 3
The value of the transfer control registers for specifying addresses and that of the DMA
command register (DCR) become undefined
The DMA status register (DSR), DMA mode register (DMR), frame end interrupt counter
(FCT), and DMA interrupt enable register (DIR) are initialized as follows:
Operating mode is single-block transfer mode
Interrupt status bits and enable bits are cleared
The FCT value is cleared and FCT is disabled
Frame end interrupt counter
2. An interrupt issued at the end of a 1-frame transfer in chained-block multi-frame transfer
3. When FCT is enabled and the FCT value is not 0000, the EOM bit is set to 1. For
1
1
Reset Operation
mode does not signal the end of a transfer.
details, see sections 6.2.7, DMA Status Register (DSR), 6.2.9, Frame End Interrupt
Counter (FCT), and 6.2.11, DMA Command Register (DCR).
Source
FCT overflow (the number of
unprocessed interrupts
Buffer underrun/overrun (EDA
value = CDA value and a new
transfer request issued)
Frame transfer completion in
chained-block transfer mode*
DMA transfer completion
16 )
2
Status Bit Enable Bit Clearing Procedure
COF
BOF
EOM
EOT
COFE
BOFE
EOME
EOTE
Rev. 0, 07/98, page 301 of 453
Write a 1 to the status bit
Write a 1 to the status bit
1.
2.
Write a 1 to the status bit
Write a 1 to the status
bit*
Issue a frame end
interrupt counter clear
command
3