HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 225

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

5.4.3
The receive clock sources are shown in figures 5.31 (a), (b), and (c). When the RXC signal is not
used as a clock source, the RXC line functions as the receive clock output line.
In asynchronous mode, the actual bit rate is determined by the clock mode (1/1, 1/16, 1/32, or
1/64). In byte or bit synchronous mode, 1/1 clock mode is automatically selected. For details, see
section 5.2.2, MSCI Mode Register 1 (MD1).
CLK
RXD line
RXC line
CLK
RXC line
(a) Receive BRG Output or RXC Line Input Used as Receive Clock
Receive Clock Sources
baud rate
generator
f
(TMC: 1 to 256, RXBR: 0 to 9)
Receive
BRG
(b) Clock Extracted by ADPLL Used as Receive Clock
baud rate
generator
Receive
=
(Receive BRG output used as the ADPLL operating clock)
TMC
f
CLK
(Receive BRG output used as receive clock)
÷ 2
f
BR
RXBR
f
(TMC: 1 to 256, RXBR: 0 to 9)
BRG
Figure 5.31 Receive Clock Sources
=
TMC
f
Receive data
ADPLL
operating
clock
CLK
f
BR
÷ 2
f
f
CLK
CLK
RXBR
: System clock (CLK) frequency
: System clock (CLK) frequency
(Sampling rate:
operating clock
8, 16, 32)
ADPLL
Clock extracted from the receive data
Rev. 0, 07/98, page 209 of 453
Receive clock
(1/1, 1/16, 1/32 or
1/64 clock mode)
Receive clock
(1/1 clock mode)