HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 270

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

6.2.10
The DMA interrupt enable register (DIR), provided for each of channels 0, 1, 2, and 3, enables or
disables transfer end interrupts, frame transfer end interrupts, buffer overflow/underflow
interrupts, and counter overflow interrupts.
Bit 7 (EOTE: Transfer End Interrupt Enable): Enables or disables a DMA normal end
interrupt (DMIB) caused by the EOT bit of DSR in either single-block transfer mode or chained-
block transfer mode as follows.
EOTE = 0: Disables an interrupt (DMIB) caused by the EOT bit
EOTE = 1: Enables an interrupt (DMIB) caused by the EOT bit
Bit 6 (EOME: Frame Transfer End Interrupt Enable): The function of this bit is described
below.
Rev. 0, 07/98, page 254 of 453
Single-block transfer mode
Notes: 1.
Single-block
transfer mode
Chained-block
transfer mode
Read/Write
Initial value
DMA Interrupt Enable Register (DIR)
Transfer end interrupt
enable
0:
1:
Disable
Enable
2.
Reserved. When read, these bits are undefined and can be set to 0 or 1.
Reserved. These bits always read 0 and must be set to 0.
Frame transfer end interrupt
enable
•
0:
1:
Chained-block transfer mode
Disable
Enable
EOTE
R/W
7
0
EOME BOFE COFE
R/W
—
6
0
*1
R/W
—
5
0
*1
Counter overflow
interrupt enable
•
0:
1:
R/W
—
4
0
Chained-block transfer mode
Disable
Enable
*1
—
—
Buffer overflow/underflow
interrupt enable
•
0:
1:
3
0
*2
Chained-block transfer mode
Disable
Enable
—
—
2
0
*2
—
—
1
0
*2
—
—
0
0
*2