HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 235

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

T
T
Figure 5.36 Noise Suppression in the Receive Data Noise Suppressor in Operating Mode 8
Receive Clock Noise Suppression: The flow of receive data, the ADPLL operating clock signal,
and the receive clock signal for noise suppression are shown in figure 5.37.
The specific operations of the ADPLL are as follows:
:
C
D
ADPLL operating clock
ADPLL operating clock
(operating mode: x 8)
Receive data
Noise-suppressed
receive data
: One ADPLL operating clock cycle
: Delay time between the receive data input to the ADPLL and the receive data after passing the
(receive BRG output)
The receive data noise suppressor receives receive data and outputs the noise-suppressed
receive data.
The ADPLL operating clock is supplied to the receive data noise suppressor and the receive
clock noise suppressor via the multiplexor.
The receive clock noise suppressor outputs the noise-suppressed receive clock .
noise suppressor and data delay unit
Receive data sampling points. The receive data is sampled at the rising edge of the ADPLL
clock pulse.
Figure 5.37 Data and Clock Signal Flow for Receive Clock Noise Suppression
(RXC line input)
Receive clock
Receive data
T
C
T
1
Multiplexor
D
(For receive data)
(For receive clock)
Noise
suppressor
2
Noise
suppressor
2 ´
Clock
extractor
Rev. 0, 07/98, page 219 of 453
Data
delay unit
Receive data
ADPLL operating clock
Receive clock
3
Noise-suppressed
receive data
Noise-suppressed
receive data