HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 91

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Note:
Read cycle
When R/W is high, if HDS or LDS is low (active) at the rising clock edge between the T
T
on the falling clock edge in the T
the T
WAIT output active high and lets the data bus float. The read cycle can be extended by
delaying the high transition of HDS or LDS.
Write cycle
When R/W is low, if HDS or LDS is low (active) at the rising clock edge between the T
T
stores the data in the register specified by the address. HDS or LDS must remain low until the
falling clock edge in the T
SCA drives the WAIT output active high.
CLK
A to A
AS
CS
HDS, LDS
D to D
(In)
R/W
WAIT
D to D
(Out)
2
3
0
1
0
states, the SCA outputs the contents of the register specified by the address on the data bus
states, the SCA latches the data on the data bus on the falling clock edge in the T
5
State numbers do not match MPU state numbers.
state. When HDS or LDS goes high (inactive), the cycle ends: the SCA then drives the
15
15
7
Figure 3.12 Slave Mode Bus Timing Sequence in CPU Mode 3
T
1
Read cycle SCA
T
Register address
2
5
state. When HDS or LDS goes high (inactive), the cycle ends: the
T
3
3
state. HDS or LDS must remain low until the beginning of
Output data
T
4
MPU
T
5
T
1
Write cycle MPU
T
2
Register address
Data latch point
T
3
Input data
Rev. 0, 07/98, page 75 of 453
T
4
SCA
T
5
3
state, and
2
1
and
and