HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 187

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

5.2.25
Current status register 0 (CST0) monitors the top stage of the MSCI's 32-stage status FIFO. This
register indicates whether or not data is in the top stage of the receive buffer, and if there is any
data, indicates the status of the data.
This register is reset under either of the following conditions:
No bit of this register generates any interrupt.
Bits 7 2: Indicate the status of the data in the top stage of the receive buffer. These bits are
arranged in the same way as bits 7 2 of the status register (ST2). When data is in the top stage of
the receive buffer, the status of the top stage of the status FIFO is set to these bits. The status is
activated when the TX/RX buffer register (TRB) is ready to be read. When data is read from
TRB, the status of the data is cleared and replaced by the status of the following data. When there
is no subsequent data, the status remains cleared.
Bit 1: Reserved. This bit always reads 0 and must be set to 0.
Bit 0 (CDE0: Current Data 0): Indicates that data is in the top stage of the receive buffer. This
bit is set to 1 when TRB is ready to be read, and is cleared when data has been read and there is no
subsequent data.
CDE0 = 0:
RX reset command
Channel reset command
System stop mode
Async
Byte sync
Bit sync HDLC
Read/Write
Initial value
Note: The bits marked with * are reserved. These bits always read 0.
MSCI Current Status Register 0 (CST0)
Indicates that no data is in the top stage of the receive buffer
Data status in the top stage of the receive buffer
EOMC0
—
R
7
0
*
SHRTC0
PMPC0
—
R
6
0
*
ABTC0
PEC0
—
R
5
0
*
FRMEC0
RBITC0
—
R
0
4
*
OVRNC0
R
3
0
CRCEC0
—
R
2
0
Rev. 0, 07/98, page 171 of 453
*
—
—
1
0
*
Current data 0
0: No data exists
1: Data exists
CDE0
R
0
0