HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 165

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

5.2.14
Interrupt enable register 0 (IE0) enables or disables the TXINT, RXINT, TXRDY, and RXRDY
interrupt requests. Interrupt requests are issued to the MPU when both the status register 0 (ST0)
bits and the corresponding bits of this register are set to 1. For details on interrupts, see section
5.7, Interrupts.
Bit 7 (TXINTE: TXINT Interrupt Enable): The function of this bit is described below.
Bit 6 (RXINTE: RXINT Interrupt Enable): The function of this bit is described below.
Asynchronous/Byte synchronous/Bit synchronous mode
TXINTE = 0: Disables an interrupt request set by the TXINT bit of ST0
TXINTE = 1: Enables an interrupt request set by the TXINT bit of ST0; a TXINT interrupt
request is issued to the MPU when the TXINT bit of ST0 is set to 1
Asynchronous/Byte synchronous/Bit synchronous mode.
RXINTE = 0: Disables an interrupt request set by the RXINT bit of ST0
RXINTE = 1: Enables an interrupt request set by the RXINT bit of ST0; a RXINT interrupt
request is issued to the MPU when the RXINT bit of ST0 is set to 1
Async
Byte sync
Bit sync HDLC
Read/Write
Initial value
Note: Bits 5–2 are reserved. These bits always read 0 and must be set to 0.
MSCI Interrupt Enable Register 0 (IE0)
TXINT interrupt
enable
0: Disable
1: Enable
TXINTE
R/W
7
0
RXINT interrupt
enable
0: Disable
1: Enable
RXINTE
R/W
6
0
—
—
5
0
—
—
4
0
TXRDY interrupt
enable
0: Disable
1: Enable
—
—
3
0
—
—
Rev. 0, 07/98, page 149 of 453
2
0
R/W
TXRDYE R XRDYE
1
0
RXRDY interrupt
enable
0: Disable
1: Enable
R/W
0
0