HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 384

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HD64570

Manufacturer Part Number
HD64570
Description
Serial Communications Adaptor
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet

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Table 10.30 CPU Mode 1 Slave Mode Bus Timing
(V
Item
Address set-up time
Address hold time
CS set-up time
CS hold time
RD active set-up time
RD inactive set-up time
RD inactive hold time
RD active hold time
WR active set-up time
WR inactive set-up time
WR inactive hold time
WR active hold time
WAIT active delay time
WAIT inactive delay time
Read data active delay time
Read data hold time
Read data floating delay time
Write data set-up time
Write data hold time
Note: The CLK timing is the same in this mode and DMA mode. See table 10.8.
Rev. 0, 07/98, page 368 of 453
CC
= 5 V
10%, V
SS
= 0 V, Ta = 40 to +85 C unless otherwise specified)
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
ADS
ADH
CSS
CSH
RDS1
RDS2
RDH1
RDH2
WRS1
WRS2
WRH1
WRH2
WTD1
WTD2
DBD1
DBD2
DBZ
DBS
DBH
Min
30
0
30
0
30
30
10
0
30
30
10
0
6
25
20
Typ
Max
50
60
60
60
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Timing
Figure 10.2

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