HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 331

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

8.1
8.1.1
The HD64570 incorporates a wait controller, which extends DMA bus cycles by inserting wait
states. This allows access to low-speed memory devices.
The wait controller has the following functional features:
8.1.2
Figure 1.5 shows the wait controller block diagram. The wait controller consists of one wait
control unit, one set of wait control registers (WCRL, WCRM, and WCRH), and one set of
physical address boundary registers (PABR0 and PABR1).
Wait state insertion using the WAIT line is accomplished by driving the WAIT line high (active).
Wait state insertion using the register is accomplished by loading WCRL, WCRM, and WCRH
with the number of wait states to be inserted.
Wait states are inserted between states T
The memory space can be partitioned into three memory areas by the boundary addresses loaded
into PABR0 and PABR1. The number of wait states inserted when each of these areas is accessed
can be specified independently for each area.
8.2
8.2.1
The physical address boundary registers 0 and 1 (PABR0 and PABR1) specify the boundaries
which divide the memory space into three areas.
Physical Address Boundary Register 0 (PABR0): Specifies the high-order eight bits of the
boundary address between the physical address low area (PAL) and the physical address middle
area (PAM). This address is the lower limit address of PAM.
Wait states can be inserted using either the WAIT line (hardware) or a register (software).
Insertion of 0 to 7 wait states is independently specified when each of three different memory
areas is accessed.
Overview
Functions
Configuration and Operation
Registers
Physical Address Boundary Registers 0, 1 (PABR0, PABR1)
Section 8 Wait Controller
2
and T
3
of a DMA bus cycle.
Rev. 0, 07/98, page 315 of 453