HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 272

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

6.2.11
The DMA command register (DCR), provided for each of channels 0, 1, 2, and 3, issues a
software abort or a frame end interrupt counter clear command to the DMAC. This register
always reads 00H.
Bits 7–2: Reserved. These bits always read 0 and can be set to 0.
Bits 1–0 (DCMD1–DCMD0: Command): The function of these bits in either single-block
transfer mode or chained-block transfer mode is described below.
DCDM1, DCDM0 = 0, 1: Issues a software abort command; initializes the corresponding DMAC
DCDM1, DCDM0 = 1, 0: Issues a frame end interrupt clear command; clears the frame end
Other settings: Inhibited
If the DMAC is disabled by software (the DE bit of DSR cleared) for a new operation, the DMAC
must be initialized by a software abort command. This is necessary because the DMAC retains its
internal state even after being disabled. However, if the DMAC was disabled when the transfer
end conditions were satisfied, a software abort command is not necessary.
Rev. 0, 07/98, page 256 of 453
Notes: 1.
Single-block
transfer mode
Chained-block
transfer mode
Read/Write
Initial value
DMA Command Register (DCR)
2.
Reserved. These bits always read 0 and must be set to 0.
These commands must not be issued when the corresponding DMAC
channel is enabled (DE = 1). No values other than those shown here
(01H and 02H) must be written to these bits.
channel (figure 6.7). All DMAC registers retain their previous values.
interrupt counter (FCT) of the corresponding DMAC channel to 0000
and the EOM bit of the DMA status register (DSR) to 0.
—
—
—
7
*1
—
—
—
6
*1
—
—
—
5
*1
—
—
—
4
*1
—
—
—
3
*1
Command specification
01:
10:
Others: Reserved
—
—
—
2
*1
Software abort
Frame end interrupt
counter cleared
DCMD1
W
—
1
DCMD0
W
—
0
*2