HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 168

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Bit 7 (UDRNE: UDRN Interrupt Enable): The function of this bit is described below.
Bit 6 (IDLE: IDL Interrupt Enable): The function of this bit is described below.
Bit 5 (CLMDE: CLMD Interrupt Enable): The function of this bit is described below.
Bit 4 (SYNCDE/FLGDE: SYNCD/FLGD Interrupt Enable): The function of this bit is
described below.
Bit 3 (CCTSE: CCTS Interrupt Enable): The function of this bit is described below.
Bit 2 (CDCDE: CDCD Interrupt Enable): The function of this bit is described below.
Rev. 0, 07/98, page 152 of 453
Asynchronous mode
Reserved. This bit always reads 0 and must be set to 0.
Byte synchronous/Bit synchronous mode
UDRNE = 0: Disables an interrupt set by the UDRN bit of ST1
UDRNE = 1: Enables an interrupt set by the UDRN bit of ST1; the TXINT bit of status
register 0 (ST0) is set to 1 when the UDRN and UDRNE bits are both 1
Asynchronous/Byte synchronous/Bit synchronous mode
IDLE = 0:
IDLE = 1:
when the IDL and IDLE bits are both 1
Asynchronous mode
Reserved. This bit always reads 0 and must be set to 0.
Byte synchronous/Bit synchronous mode
CLMDE = 0: Disables an interrupt set by the CLMD bit of ST1
CLMDE = 1: Enables an interrupt set by the CLMD bit of ST1; the RXINT bit is set to 1
when the CLMD and CLMDE bits are both 1
Asynchronous mode
Reserved. This bit always reads 0 and must be set to 0.
Byte synchronous/Bit synchronous mode
SYNCDE/FLGDE = 0:Disables an interrupt set by the SYNCD/FLGD bit of ST1
SYNCDE/FLGDE = 1:Enables an interrupt set by the SYNCD/FLGD bit of ST1; the RXINT
bit of ST0 is set to 1 when the SYNCD/FLGD and SYNCDE/FLGDE bits are both 1
Asynchronous/Byte synchronous/Bit synchronous mode
CCTSE = 0: Disables an interrupt set by the CCTS bit of ST1
CCTSE = 1: Enables an interrupt set by the CCTS bit of ST1; the TXINT bit of ST0 is set to
1 when the CCTS and CCTSE bits are both 1
Disables an interrupt set by the IDL bit of ST1
Enables an interrupt set by the IDL bit of ST1; the TXINT bit of ST0 is set to 1