HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 119

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

(ST2), 5.2.25, MSCI Current Status Register 0 (CST0), and 5.2.26, MSCI Current Status Register
1 (CST1).
Input data is received via the RXD line and enters the MSCI internal circuitry after passing
through a decoder. The data path inside the MSCI differs according to the operating mode
(asynchronous, byte synchronous, or bit synchronous).
In asynchronous mode, the MSCI checks input data for the parity/MP bit and for framing errors
before passing it to receive shift register 4. When one character of data is received, the data is sent
to the receive buffer. The MPU or DMAC can read the data from the receive buffer (TX/RX
buffer register (TRB)) via the internal data bus. Note that the TX/RX buffer register (TRB) is
located at the top of the receive buffer and interfaces with the internal data bus. For details, see
section 5.2.21, MSCI TX/RX Buffer Register (TRB).
In byte synchronous mode, input data enters receive shift register 1 before branching toward
receive shift register 2 and receive shift register 4.
The data received by receive shift register 2 is used to detect SYN character(s). The data received
by receive shift register 4 is transmitted to the receive buffer, and is also transmitted to the RX
CRC calculator, for CRC calculation, via the RX delay register and RX CRC shift register.
Output from the CRC calculator goes to status register 2 (ST2). The MPU or DMAC can read the
received data and its status.
In bit synchronous mode, input data enters receive shift register 1, which deletes 0s, and detects
flags, abort status, and idle status. The data then branches toward receive shift register 2 and the
RX CRC calculator. Output from the CRC calculator is sent to ST2, as in byte synchronous mode,
and is also sent to the frame status register (FST) at the completion of frame reception. In other
words, FST always holds the status of the most recently received frame.
The data sent to receive shift register 2 is sent via receive shift registers 3 and 4 to the receive
buffer if the data's secondary station address detected coincides with the present station (SCA)
address. The MPU or DMAC can read the received data and its status via the internal data bus.
When CRC calculation is disabled (the CRCCC bit of mode register 0 (MD0) is 0), the received
data is sent directly from receive shift register 1 to receive shift register 4. The secondary station
address is also detected in this case.
Transmitter: The following describes the operations of the MSCI transmitter, referring to figure
1.11.
The MSCI transmitter has one 32-stage FIFO transmit buffer, one transmit shift register, and one
TX pattern register. The transmitter also has one CRC calculator, as the receiver does.
The MPU or DMA writes output data via the internal data bus to the transmit buffer (TX/RX
buffer register (TRB)). Information necessary to assemble frames in each communications mode
Rev. 0, 07/98, page 103 of 453