HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 186

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

5.2.24
TX ready control register 1 (TRC1) determines the MSCI TX ready (TXRDY) inactivation
condition. The function of this register is the same in asynchronous, byte synchronous, and bit
synchronous modes.
Bits 7 5: Reserved. These bits always read 0 and must be set to 0.
Bits 4 0 (TRC14 TRC10: TX Ready Control 1): Determine the MSCI TX ready (TXRDY)
inactivation condition. When the data byte count in the transmit buffer is equal to or greater than
TXF1 + 1, that is, the value set by these bits + 1, TX ready is inactivated. In other words, the
TXRDY bit of status control register 0 (ST0) is set to 0. Any value can be set in the range from
00H 1FH. Note that TX ready is inactivated (the TXRDY bit of ST0 is set to 0) when the data
byte count in the transmit buffer is equal to or greater than TXF1 + 1, under the condition that
TXF1 is less than TXF0 (the value set by TRC04 TRC00 bits of TX ready control register 0
(TRC0)).
Rev. 0, 07/98, page 170 of 453
MSCI TX Ready Control Register 1 (TRC1)
Async
Byte sync
Bit sync HDLC
Read/Write
Initial value
Note: Bits 7–5 are reserved. These bits always read 0 and must be set to 0.
—
—
7
0
—
—
6
0
—
—
5
0
R/W
TRC14
4
1
TX ready control 1 (TXF1)
TRC13 TRC12 TRC11 TRC10
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1