HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 80

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Figure 3.4 shows the interconnections of the bus arbiter and bus masters.
3.3.2
If BUSACK becomes inactive (high) (HOLDA becomes low in CPU mode 0) during a DMA
transfer, the bus arbiter releases control of the bus at an opportunity furnished by the on-chip
DMAC controller.
The on-chip DMAC controller allows control of the bus to pass to another bus master at the end of
each machine cycle, immediately after a T
BUSACK (HOLDA in CPU mode 0) becomes inactive, the on-chip DMAC suspends the transfer
at the end of a machine cycle and makes BUSY inactive (high), passing control of the bus to
another bus master. If BUSACK (HOLDA in CPU mode 0) later becomes active low (high in
CPU mode 0), the DMAC waits for BUSY to become inactive, then takes control of the bus and
resumes the transfer.
3.3.3
Figure 3.5 shows how bus control is passed.
Rev. 0, 07/98, page 64 of 453
Timing for Passing Bus Control
Bus Control Passing
DMAC
Figure 3.4 Bus Arbiter and Bus Masters
arbiter
SCA
Bus
Data bus and address bus
Bus control signals
HOLD/
BUSREQ
HOLDA/BUSACK
3
or T
BUSY
BEO
i
state. See section 6, DMAC, for details. When
(DMAC: DMA controller)
MPU
Bus
request
Other bus
master