HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 76

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

From the normal operating mode it is possible to enter any other chip operating mode, as follows:
3.2.5
Setting the IOSTP bit in the low-power register (LPR) to 1 puts the SCA into system stop mode.
System stop mode is a low-power mode in which clock signals are not supplied to the on-chip
functional modules.
Operation in System Stop Mode: In system stop mode, the SCA operates as follows:
Power dissipation in system stop mode can be further decreased by stopping external clock input.
The external clock input line (CLK) should be held high (low in CPU mode 0). The SCA is not
guaranteed to operate as described above if clock input stops in the low state (high in CPU mode
0).
Entering and Leaving System Stop Mode: Enter system stop mode from the normal operating
mode by setting the IOSTP bit in the low-power register (LPR) to 1. The mode transition takes
place during the write cycle in which IOSTP is set to 1. Figures 3.3 (a) to (d) show the timing.
The SCA leaves system stop mode by entering reset mode.
Rev. 0, 07/98, page 60 of 453
If the RESET signal is active for six clock cycles or more, the SCA enters reset mode.
If the IOSTP bit is set to 1, the SCA enters system stop mode. IOSTP is bit 0 of the low power
register (LPR). See section 3.2.5, System Stop Mode, for details.
The MSCI, DMAC, and timers halt.
The bus interface shuts down. Registers cannot be written or read.
The on-chip clock generator circuit continues to operate, but no clock signals are supplied to
the main functional modules.
Pins are placed in the states listed in table 3.2.
System Stop Mode