HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 81

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Notes:
Figure 3.6 shows examples of bus arbitration sequences. The following describes the sequence in
CPU modes 1 to 3 when the system is configured as shown in figure 3.7. The differences between
CPU mode 0 and other modes are that in CPU mode 0, HOLD and HOLDA are used instead of
BUSREQ and BUSACK, respectively, and that the HOLD, HOLDA, and CLK signals have the
opposite phase to their counterparts in the other modes. For details on DMA cycles, see Section
6.4, Operating Modes.
Figure 3.6 (a) shows the bus arbitration sequence in which the master MPU has control of the bus,
that is, the BUSY input is high. In this sequence:
In this case, when a DMA transfer is requested in the SCA, the SCA drives BUSREQ active at the
next falling edge of CLK to request control of the bus from the master MPU. The SCA then
samples the BUSACK input from the master MPU at each rising edge of CLK. Here, the SCA also
samples the BUSY input to check whether or not any other bus master is using the bus (BUSY is
(a)
and the master MPU, in response, grants control of the bus to the SCA by driving BUSACK
active (low).
(b) The SCA passes control of the bus to another bus master with BUSACK kept active
because another bus master requests for control of the bus.
1.
2.
3.
4.
The SCA requests the master MPU to release the bus by driving BUSREQ active (low),
Reset
mode
RESET = 0
See section 6, DMAC for information about DMA requests.
If the RESET signal is driven active low for six cycles or more, the SCA
unconditionally enters reset mode. When RESET goes high, the SCA enters
normal operating mode and control of the bus passes to the MPU (or an external
bus master), leaving the SCA in slave mode.
Slave mode is the mode in which the MPU or external bus master has control of
the bus. The SCA executes MPU read/write cycles and interrupt acknowledge
cycles in this mode.
In master mode, the SCA has control of the bus and can execute DMA transfers.
*2
Figure 3.5 Bus Control Passing
RESET = 1
RESET = 0
No DMA request
or BUSACK = 1
(HOLDA = 0 in
CPU mode 0)
Master
mode
*4
*1
DMA request
BUSACK = 0
(HOLDA = 1 in CPU mode 0)
Slave
mode
Rev. 0, 07/98, page 65 of 453
*3
*1
and