HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 243

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Table 5.20 gives widths and duty ratios (pulse width to pulse period) of BRG output clock
waveforms along with the corresponding register set values.
Table 5.20 BRG Output Waveform and Register Set Values
Set Value
BR
1 9
0
BR:
TMC: Value of bits 7 0 of the TMC
5.6.3
Asynchronous Mode: In asynchronous mode, the bit rate is selected with TMC7 TMC0 bits of
the time constant register (TMC), the TXBR3 TXBR0 bits of the TX clock source register (TXS),
TMC
= 1
Value of bits 3 0 of the TXS or RXS
f
f
ADPLL operating clock)
TMC:
BR:
1
BRG
CLK
Register Set Values and Bit Rates
:
:
Waveform
Duty ratio = 50%
Duty ratio = 50% when TMC = 2
Duty ratio
Duty ratio = 50%
Cycle width is 1 system clock cycle
Transmit (receive) BRG output frequency
System clock frequency (frequency equal to f
Value (1 256) set in TMC
Value (0 9) of TXBR3 TXBR0 bits of TXS or RXBR3 RXBR0 bits of RXS
TMC
50% when TMC
2
Pulse width is 1 system clock cycle
BRG
Rev. 0, 07/98, page 227 of 453
can be used only for the
1 system
clock cycle
1 system
clock cycle