HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 282

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Table 6.3
Operating Mode*
Requesting source
Data transfer unit
Bus mode
Minimum transfer states/byte
(Word)
Operation Source
Available MSCI modes
Notes: 1. The operating mode is specified using the AMOD and TMOD bits of the DMA mode
Rev. 0, 07/98, page 266 of 453
2. Normal operation is not guaranteed in asynchronous or byte synchronous mode.
address
Destination
address
Transfer
end
condition
register (DMR). For details, see section 6.2.8, DMA Mode Register (DMR).
DMAC Operating Modes
1
Normal
end
Error
end
Memory to
MSCI
MSCI
Single block
Started by a request from the MSCI
A request from the MSCI is level sensitive
3 states
Specified by
the source
address
register (SAR)
MSCI
transmitter
The number of bytes of data
specified in the byte count
register (BCR) has been
transferred
Asynchronous, byte
synchronous, or bit
synchronous
Single-Block Transfer Mode
(Single Address)
MSCI to
Memory
MSCI receiver Specified by the buffer address
Specified by
the destination
address
register (DAR)
Single Frame
Transfer
Single frame
register (BAR)
MSCI transmitter
One frame has
been
transferred
A DMA transfer request is issued when the error descriptor
address register (EDA) and current descriptor address register
(CDA) match
Frame end interrupt counter (FCT) overflows when it is
enabled
Bit synchronous*
Chained-Block Transfer Mode (Single Address)
Memory to MSCI
Multi-Frame
Transfer
Multi-frame
The frame
specified by the
descriptor
status field
(ST) has been
transferred
2
Multi-Frame
Transfer
Single frame
MSCI receiver
Specified by BAR
One frame
has been
transferred
MSCI to Memory
Multi-Frame
Transfer
Multi-frame