HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 86

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HD64570

Manufacturer Part Number
HD64570
Description
Serial Communications Adaptor
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet

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3.4
3.4.1
The SCA has four 8- and 16-bit bus interfaces that can be switched under external control. The bus
interface is selected according to the CPU mode as shown in table 3.3.
Table 3.3
CPU Modes Bus
Mode 0
Mode 1
Mode 2*
Mode 3*
Notes: 1. CPU modes 2 and 3 differ only in the bus timing. See section 10, Electrical
The SCA has three 16-bit bus interfaces (CPU modes 0, 2, 3). The high-byte/low-byte address
relationship on the data bus in CPU mode 0 is opposite to the relationship in CPU modes 2 and 3.
This gives the SCA a byte-swap capability. The data bus lines map onto even and odd memory
banks as shown in figure 3.8.
Rev. 0, 07/98, page 70 of 453
2. Number of states in read cycle/number of states in write cycle
3. Number of states for consecutive bus cycles in slave mode
4. When no wait states are inserted.
5. Shortest number of states. The number of states may increase if the MPU's strobe
1
1
Bus Interface
Overview
Characteristics for details.
disable timing is delayed.
Width
16 bits
8 bits
16 bits
16 bits
CPU Mode and Bus Interface
High Byte
(D15 to D8)
Odd address
Even address
Even address
Address Relationships
of Data Bus
Low Byte
(D7 to D0)
Even address
All addresses
Odd address
Odd address
Slave
Mode*
4 (5)*
4/5
5/6
5/5
Length of Bus Cycle
(number of states)
3
/4 (5)*
2,
*
5
3
Master
Mode
3*
3*
3*
3*
4
4
4
4
MPU Type
8086-system
16-bit MPU
64180-type
MPU
68000-system
16-bit MPU I
68000-system
16-bit MPU II

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