HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 217

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Note:
Error Checking: Involves the following items.
CRC errors
In bit synchronous HDLC mode, CRC-CCITT is usually used. Its initial value is all 1s, which
can be specified with the CRC1 CRC0 bits of MD0. (The CRC polynomial is X
+ 1 for CRC-CCITT.)
The transmitter and receiver both have a CRC calculator.
The CRC calculator is automatically initialized immediately before the A field transmission or
reception.
During transmission, CRC calculation is carried out on the data in the A, C, and I fields before
zero insertion.
Use the CRCCC bit of MD0 and the end of message command to enable CRC code
transmission. The CRC code is transmitted automatically when both the CRCCC bit and the
UDRNC bit of CTL are set to 1 in underrun state. For details, see section 5.2.1, MSCI Mode
Register 0 (MD0), section 5.2.4, MSCI Control Register (CTL), and section 5.2.8, MSCI
Command Register (CMD).
Flag wait state
Figure 5.28 State Transition Diagram for Reception in Bit Synchronous Mode
"RX enable"
issued
Command names are enclosed in double quotation marks (“ ”)
Initialization by reset
Flag
detected
Abort
detected
Flag detected
disable
state
RX
Character
wait state
Flag detected
within 3-character
time (short frame)
1. Abort detected
2. "Message reject" issued
Flag detected (frame detected)
Data (other than
flag and abort)
received
"RX disable", "RX reset", or "Channel reset"
issued in any state
field check
Address
state
1. NG
2. Abort detected
Rev. 0, 07/98, page 201 of 453
OK
1. Flag or abort not
2. "Message reject"
receive state
Character
detected
not issued
16
+ X
12
+ X
5