HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 253

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Table 5.23 Interrupts, Interrupt Sources, and Clearing Procedures (cont)
Interrupt
Type
RXINT
interrupt
Clearing procedure 1:
Clearing procedure 2:
Clearing procedure 3:
Clearing procedure 4:
Notes: 1. The RXINT interrupt source can also be cleared by a channel reset or an RX reset
2. Status register 2 (ST2) bit values are transferred to the frame status register (FST) and
3. In CPU mode 1, the PMP bit is cleared when the parity/MP bit of the next data is 0,
4. CRC calculation result can be read from the CRCE bit when the CRCCC bit of mode
command. The TXRDY and TXINT interrupt sources can also be cleared by a channel
reset or a TX reset command.
ST2 is reset when the last character has been read from the receive buffer at
completion of receive frame transfer.
(when the next data becomes ready to be read). In CPU modes 0, 2, and 3, this bit is
cleared when the parity/MP bit of the next two bytes of data are both 0 (when the next
two bytes of data become ready to be read).
register 0 (MD0) is 1. For details on the setting/resetting timing of the CRCE bit, see
Error Checking, in section 5.3.2, Byte Synchronous Mode; and Error Checking, in
section 5.3.3, Bit Synchronous Mode.
Interrupt
Status
Bit
RXINT
Enable
Bit
RXINTE
Write data to the transmit buffer until the data byte count in the buffer
becomes equal to or greater than TXF + 1, (TXF is the value specified with
TX ready control register 1 (TRC1)), or disable the transmitter.
Read data from the receive buffer until it becomes empty.
(1), (3) : Write a 1 to each status bit.
(2):Write data to the transmit buffer to place the transmitter in other state.
(1)
PMP:
CRCE:
(12): Write a 1 to each status bit.
Interrupt Source
(9)Overrun error
(10)CRC error
(11)End of message
(12)Two-clock missing
Read data from the receive buffer to enable reading the next
data*
Automatically cleared when the CRC calculation result is
normal*
(FST)
detection
3
.
4
.
Source
Status Bit
OVRN*
CRCE*
EOMF
CLMD
Rev. 0, 07/98, page 237 of 453
2
2
Enable
Bit
OVRNE
CRCEE
EOMFE
CLMDE
Clearing
Procedure*
4
1