HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 287

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Keep the following in mind about the timing in this transfer mode.
6.4.3
Operation: In memory-to-MSCI chained-block transfer mode, frame-bounded data is DMA-
transferred in byte or word units from a system memory buffer to the MSCI in bit synchronous
mode. Transfer requests are initiated by the MSCI internal signal. Note that chained-block
transfer mode is not available with the MSCI operated in asynchronous or byte synchronous mode.
Memory-to-MSCI transfer employs DMAC channels 1 and 3. For this transfer mode, follow the
steps below starting with the DMA in its initial state. (Steps 1 to 5 may be completed in any
order.)
1.
2.
3.
4.
5.
6.
Memory-to-MSCI chained-block transfer mode is shown in figure 6.13.
Transfer requests are issued using the MSCI signal.
Wait states can be inserted between T
memory write cycle), using the WAIT line or the wait controller registers.
One T
(CPB). Since the CPB value is fixed during operation, descriptors can be assigned to any
consecutive 64-Kbyte area in system memory.
next to the last transmit buffer, into the error descriptor address register (EDA).
transmit buffer, into the current descriptor address register (CDA).
descriptor.
starts when the DMAC obtains the bus control.
Specify chained-block transfer mode with the DMA mode register (DMR).
Load the high-order eight bits of the 24-bit descriptor address into the chain pointer base
Load the low-order 16 bits of the start address of the descriptor, which indicates the buffer
Load the low-order 16 bits of the start address of the descriptor, which indicates the first
Initialize the chain pointer (CP), buffer pointer (BP), data length (DL), and status (ST) in each
After steps 1 to 5, set the DE bit of the DMA status register (DSR) to 1. DMA operation
i
Memory-to-MSCI Chained-Block Transfer Mode
clock cycle is inserted before the first byte or word is transferred.
2
and T
3
states in each bus cycle (memory read cycle and
Rev. 0, 07/98, page 271 of 453