HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 238

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

When the transmit clock (TXC) is generated by the internal baud rate generator, if BR = 0 and
TMC > 2, then as shown in table 5.12, the duty cycle of TXC is not 50%, so the duty cycle of the
signal on TXD is not 50%. When the receiving device inputs this signal on its RXD line, the
ADPLL does not extract the clock or sample the data correctly. For this reason, transmitter
settings with BR = 0 and TMC > 2 should be avoided.
When an FM-type code is received, normally the ADPLL is used to extract the clock component
from the RXD input, then the data is sampled using the extracted receive clock. There is
accordingly no need to supply a receive clock on the RXC line, but an operating clock must be
supplied to the ADPLL.
It is possible to receive FM-type encoded data using a receive clock input via RXC, without using
the ADPLL. In this case the receive data is sampled on the rising edges of the RXC receive clock,
as in reception of NRZ-type encoded data, so attention must be paid to the phase relationship
between RXC and RXD. With FM0 or FM1 encoding, the data can be received by latching the
value in the second half of the bit cell. For Manchester encoding, the data can be received by
latching the value in the first half of the bit cell. Figure 5.41 shows these timing relationships.
Since they differ from the timing shown in figure 5.40, in communication between two SCA's, an
external circuit must adjust the phase relationship between the transmit clock and transmit data.
Rev. 0, 07/98, page 222 of 453
TXC
TXD
RXD
RXC
(a) FM0 or FM1 Encoding
(a) FMO and FMI
One bit cell
One bit cell
Figure 5.40 Transmit Timing for FM-Type Codes
Figure 5.41 Receive Timing for FM-Type Codes
Latch data in
second half-cell
TXC
TXD
RXD
RXC
(b) Manchester Encoding
(b) Manchester
One bit cell
One bit cell
Latch data in
first half-cell