HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 234

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

T
T
T
T
T
The receive data noise suppression timing in the noise suppressor is shown in figure 5.36. NRZ
code receive data is used in this example. The same basic timing also applies to other codes.
The ADPLL samples receive data at the rising edge of the ADPLL operating clock pulse. In
operating mode
data. (The same data level sampled three times in succession in operating mode 16 and five
times in succession in operating mode
suppressed as noise.
Å, Ç, and É in the figure correspond to "On", "Off", and "Undefined" in No. 4 of table 5.16,
ADPLL Specifications. É is suppressed as noise since the same level cannot be sampled twice in
succession.
Rev. 0, 07/98, page 218 of 453
ADPLL operating clock
(Operating mode: x 8)
Receive data
Extracted clock
Receive data syncronized
with the extracted clock
B
C
D
S-1
S
:
:
:
:
and T
Figure 5.35 FM0 Receive Data Phase Compensation in Operating Mode 8
S-2
: Receive data level transitions after noise suppression
One receive data bit time
One ADPLL operating clock cycle
Delay time between the receive data input to the ADPLL and the receive data after
passing the noise suppressor and data delay unit
Synchronized transitions of noise-suppressed receive data after noise suppression.
8, the same receive data level sampled twice in succession is considered valid
T
D
T
B
T
T
32 is considered valid data.) All other sampled data is
S-2
C
T
S-1
T
T /4
S
B
T /2
B
T /4
B
T
S