HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 256

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

The DMAC supports single-block transfer mode (single address) and chained-block transfer mode,
both of which control DMA transfers between the on-chip MSCI and memory.
In either mode, a DMA transfer is initiated by a transfer request received when the DMA is
enabled after the DMAC's internal registers have been loaded with the required values in DMA
initial state.
Single-Block Transfer Mode: The DMAC transfers one word or one byte of data between
memory and the MSCI in each memory read or memory write cycle, using the single addressing
mode. After having transferred the specified number of bytes (up to 64 Kbytes), the DMAC
returns to DMA initial state.
Because the DMAC channels 0 and 2 are hardwired to the MSCI receivers and channels 1 and 3 to
the MSCI transmitters, the transfer direction for each channel is fixed: from the MSCI to memory
for channels 0 and 2, and from memory to the MSCI for channels 1 and 3.
Transfer requests are generated by a request signal indicating the status of the MSCI
receive/transmit buffers.
Chained-Block Transfer Mode: When the MSCI is in bit synchronous mode, the DMAC
transfers one word or one byte of frame-bounded data between memory and the MSCI in each
memory read or memory write cycle, using the single addressing mode. After having transferred
frame(s), the DMAC returns to DMA initial state. Note that normal operation is not guaranteed
for chained-block transfer mode initiated in modes other than bit synchronous mode.
The transfer direction for each channel is fixed: from the MSCI to memory for channels 0 and 2,
and from memory to the MSCI for channels 1 and 3.
In this mode, it is always necessary to assign the required buffers and descriptors in memory
before transfer operations, regardless of the transfer direction. The user may assign as many
buffers as required, linking the buffers in a chain form with the descriptors. Thus, the user must
load the starting address of the buffer and the next descriptor into each descriptor.
For an MSCI-to-memory transfer, loading the necessary values into the DMAC registers and then
enabling the DMA causes the DMAC to write data sequentially to the receive buffer in memory.
For a memory-to-MSCI transfer. The same events cause the DMAC to read the data sequentially.
Even while the DMA is enabled, buffers whose contents have already been read/written can be
released and used for new data. This enables transfer of successive data frames.
Transfer requests are generated by an internal request signal indicating the status of the MSCI
receive/transmit buffers.
Rev. 0, 07/98, page 240 of 453