HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 28

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

1.6.3
Register Name
TX/RX buffer register
RX ready control register RRC
TX ready control register 0 TRC0
TX ready control register 1 TRC1
Current status register 0
Current status register 1
Notes: 1. These initial values apply after a hardware reset or execution of a channel reset
1.6.4
Register Name
DMA priority control
register
DMA master enable
register
Note: Use byte access to read and write PCR and DMER. These registers cannot be accessed by
Rev. 0, 07/98, page 12 of 453
word access.
2. The functions of some bits vary depending on the operating mode (asynchronous, byte
3. The TX/RX buffer register (TRBL, TRBH) acts as the receive buffer register for the
MSCI Registers (2)
DMAC Registers Common to Channels 0 to 3
command. Some registers are also initialized to these values by the RX reset command
or TX reset command. See section 5.2, Registers, for details.
synchronous, or bit synchronous). See the register descriptions starting in section 5.2.1.
received character when read, and as the transmit buffer register for the transmitted
character when written.
Symbol
PCR
DMER
Symbol Channel 0 Channel 1 Channel 0 Channel 1 MSB
TRBL
TRBH
CST0
CST1
20H
21H
3AH
38H
39H
3CH
3DH
CPU Modes
0 & 1
08H
09H
CPU Modes 0 & 1
40H
41H
5AH
58H
59H
5CH
5DH
Address
Address
CPU Modes
2 & 3
09H
08H
21H
20H
3BH
39H
38H
3DH
3CH
CPU Modes 2 & 3
41H
40H
5BH
59H
58H
5DH
5CH
Initial Value at Hardware Reset
MSB
0
1
0
0
0 0
0 0
0 0
0 0
0 0
0
0
Initial Value at Reset*
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
LSB
LSB
1
0
0
1
0
0
0
0
Read/W
rite
R/W*
R/W*
R/W
R/W
R/W
R/W
R/W
Read/
Write
R/W
R/W
3
3