HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 92

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

3.4.3
In master mode (DMA mode), data moves from memory to the SCA in a read cycle, and from the
SCA to memory in a write cycle. The address and bus interface signals are output signals, except
for WAIT which is an input signal.
Word Transfer from Odd Address: In CPU modes 0, 2, and 3, DMA transfer of a word starting
at an odd address is performed as two byte transfers. The DMAC first transfers one byte from the
odd address, then transfers the remaining byte from the succeeding even address. Figure 3.13
shows how a word is transferred from an odd address.
Word Transfer from Even Address: In CPU modes 0, 2, and 3, a word is transferred from an
even address by direct memory access in a single word transfer operation.
Rev. 0, 07/98, page 76 of 453
2n + 3
2n + 1
D
Master Mode Bus Cycle
15
First transfer
—
(a) CPU Mode 0
D
8
Figure 3.13 Word Transfer from Odd Address
D
Next transfer
7
—
D
0
2n + 2
2n
2n + 2
2n
D
Next transfer
15
(b) CPU Modes 2 and 3
—
2n, 2n + 1,
D
8
D
7
First transfer
—
are addresses
D
0
2n + 3
2n + 1